This page contains a set of notes about the ARM Generic Interrupt Controller v3.

Interrupt Types:

  • SPI: Shared Processor Interrupts -- most hw interrupts; e.g. uarts
  • PPI: Per-Processor Interrupts -- interrupt caused by hw attached to one core, e.g. timers
  • SGI: Software-Generated Interrupts -- interrupt caused by another core
  • LPI: Locality-specific Peripheral Interrupt -- ???, new in GICv3

Interrupt Numbers:

  • 0-15: SGIs
  • 16-31: PPIs
  • 32-1019: SPIs
  • 1020-1023: Special
  • 1024-1055: Reserved
  • 1056-1119: PPIs
  • 1120-4095: Reserved
  • 4096-5119: SPIs
  • 5120-8191: Reserved
  • 8192-???: LPIs

Affinity Routing:

PEs (cores) identified by a dotted-quad (like IPv4). In AArch32, the top octet is 0. The current core's affinity value can be read from the MPIDR_EL1 register, which also has other relevant flags.

Registers (3 Parts):

  • Distributor Interface: One per GIC
    • Routes SPIs and SGIs
  • Redistributor Interface: One per core
  • CPU Interface: One per core

Interrupts can be disabled/enabled with GICR_ICENABLER<n>/GICR_ISENABLER<n> registers; reading from each gets the same value, but writing to IC clears the positions with 1 bits, while IS sets the positions with 1 bits.


  • Interface Control Register
  • Interface Priority Mask Register
  • Interrupt Acknowledge Register
  • End of Interrupt Register